About This Book
The MindShare Architecture Series....1
Organization of This Book.....2
Part One – The EISA Specification....2
- EISA Overview.....2
- EISA Bus Structure Overview.....2
- EISA Bus Arbitration.....2
- Interrupt Handling.....2
- Detailed Description of EISA Bus.....3
- ISA Bus Cycles...3
- EISA CPU and Bus Master Bus Cycles.....3
- EISA DMA....3
- EISA System Configuration.....3
Part Two – The Intel 82350DT EISA Chipset.....3
- EISA System Buses.....3
- Bridge, Translator, Pathfinder, Toolbox...3
- Intel 82350DT EISA Chip Set...4
Who This Book Is For.....4
Prerequisite Knowledge...4
Documentation Conventions....4
- Hex Notation....5
- Binary Notation....5
- Decimal Notation....5
- Signal Name Representation.....5
- Bit Field Identification (logical bit or signal groups)....5
We Want Your Feedback.....6
Bulletin Board...6
Mailing Address....6
Part One – EISA Specification
Chapter 1: EISA Overview
Introduction...9
- Compatibility With ISA...10
- Memory Capacity...10
v EISA System Architecture
Synchronous Data Transfer...